您可能会好奇，新一代处理器如何能够在与旧处理器相同的时钟速度下更快。这仅仅是物理结构上的变化还是更多的变化？今天的超级用户问答帖子回答了一位好奇的读者的问题。

今天的问答环节是由SuperUser提供的，SuperUser是Stack Exchange的一个分支，是一个由社区驱动的问答网站分组。

图片由罗德里戈·塞纳（Flickr）提供。

问题

超级用户读者agz想知道为什么新一代处理器在相同的时钟速度下更快：

Why, for example, would a 2.66 GHz dual-core Core i5 be faster than a 2.66 GHz Core 2 Duo, which is also dual-core?

Is this because of newer instructi*** that can process information in fewer clock cycles? What other architectural changes are involved?

为什么新一代处理器在相同的时钟速度下速度更快？

答案

超级用户贡献者davidschwartz和Breakthrough为我们提供了答案。首先，大卫·施瓦茨：

Usually, it is not because of newer instructi***. It is just because the processor requires fewer instruction cycles to execute the same instructi***. This can be for a large number of reas***:

1. Large caches mean less time wasted waiting for memory.
2. More execution units means less time waiting to start operating on an instruction.
3. Better branch prediction means less time wasted speculatively executing instructi*** that never actually need to be executed.
4. Execution unit improvements mean less time waiting for instructi*** to complete.
5. Shorter pipelines means pipelines fill up faster.

And so on.

接着是突破的答案：

The absolute definitive reference is the Intel 64 and IA-32 Architectures Software Developer Manuals. They detail the changes between architectures and they are a great resource to understand the x86 architecture.

I would recommend that you download the combined volumes 1 through 3C (first download link on the page linked above). Volume 1, Chapter 2.2 has the information you want.

Some general differences listed in that chapter, going from the Core to the Nehalem/Sandy Bridge micro-architectures are:

• Improved branch prediction, quicker recovery from misprediction
• HyperThreading Technology
• Integrated memory controller, new cache hierarchy
• Faster floating-point exception handling (Sandy Bridge only)
• LEA bandwidth improvement (Sandy Bridge only)
• AVX instruction extensi*** (Sandy Bridge only)

The complete list can be found in the link provided above (Volume 1, Chapter 2.2).

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